At the 2025 RISC-V Summit in China, Nvidia announced that its CUDA software platform will be made compatible with the RISC-V instruction set architecture (ISA) on the CPU side of things. The news was ...

Open source software is popular – for operating systems as well as for office programs. But can this idea also work with hardware? We interviewed Rick O'Connor, Executive Director of the RISC-V ...

IDE Supporting All 32-bit RISC-V Implementations to be Presented at 54th Design Automation Conference in Austin, Texas on June 20 ALISO VIEJO, Calif., Jun. 15, 2017 – Microsemi Corporation (Nasdaq: ...

The members of the RISC-V Foundation have agreed on the new instruction set profile RVA23. Compared to older profiles such as RV64GC, it describes a greatly expanded mandatory functional scope of ...

This new technical paper titled “Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms” was published by researchers at Intel, North Arizona University and Google, with ...

A job listing posted to Apple's website this week reveals the company is researching RISC-V instruction set architecture solutions, suggesting future in-house chip designs might implement the ...

The Risc instruction set started life in the University of California, Berkley, almost a decade ago. It has since blossomed into a bunch of 32- and 64-bit instruction sets, managed and protected by ...

First and foremost, RISC-V is a modular, open-source, instruction set definition and nothing more. RISC-V as an ecosystem is much more. The instruction set provides the encoding and semantics, but it ...

Microsemi Corporation, a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, announced the release of its SoftConsole version 5.1, the world’s ...