EDN

Phase noise and jitter — a primer for digital designers

As clock speeds in communications systems push into the GHz range, phase noise and jitter — always key issues in analog designs — are becoming increasingly critical to the performance of digital chips ...
EDN

Phase noise cancellation in high-speed data converter systems

Editor’s note: I am pleased to introduce this month’s guest TI author, Robert Keller, Systems Manager in TI’s High-Speed Products group. He has 15 years of experience supporting high-speed products in ...
Nature

Noise-Shaping Successive Approximation Register Analog-to-Digital Converters

The noise‐shaping successive approximation register (NS‐SAR) analogue‐to‐digital converter represents an attractive hybrid architecture that merges the inherent energy efficiency and simplicity of ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 1)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...