Design Rule Checks (DRC) - A Practical View for 28nm Technology
WEBThis whole process is called Design Rule Checking (DRC). There are many design rules at different technology nodes, a few of which are mentioned below. Types of DRCs: Minimum width and spacing for metal. Minimum width and spacing for via. Fat wire Via keep out Enclosure. End of Line spacing. Minimum area.
System Verilog Macro: A Powerful Feature for Design Verification …
WEBSV macro is one of the most powerful features out there and if used properly with a thorough understanding and applied wisely in a DV project, it can help to save a lot of time and can make the code more readable and efficient. This paper shows how, using SV macro with the proper syntaxes, a DV engineer can break up the larger complex code in smaller chunk and can reuse it at many places.
Understanding Logic Equivalence Check (LEC) Flow and Its …
WEBLogic Equivalence Check, popularly known as LEC is one of the most important parts of the ASIC VLSI design. Formal verification techniques have been developed using mathematical proof rather than simulation or test vectors to provide a higher level of verification confidence on properties. For example, the implementation can be either a Verilog ...
Enhancing VLSI Design Efficiency: Tackling ... - Design And Reuse
WEBThe objective of this paper is to illustrate congestion, shorts, and practical approaches to fix both issues at lower/higher technology nodes. This paper also includes PnR tool (ICC2) related commands and their uses to overcome the mentioned issues.
Understanding Shmoo Plots and Various Terminology of Testers
WEB3. Wall Shmoo. Wall Shmoo depicts a failure at a certain voltage irrespective of any variation in frequency. This kind of Shmoo leads to indicate the problem of noise coupling, race condition, and charge sharing. The noise can be aggravated by higher di/dt (higher inductance) and dv/dt (higher capacitive coupling).
Demystifying MIPI C-PHY / DPHY Subsystem - Design And Reuse
WEBFor D-PHY this can be accomplished by using four-lane D-PHY, using 10 wires, each Lane running at 1.0Gbps/lane. To obtain the same aggregate data rate at the same or lower transition rate with C-PHY, we can use two-lanes C-PHY, with 6 wires, running at 0.875Gsps, which is less than the 1.0Gsps for the D-PHY.
UVM RAL Model: Usage and Application - Design And Reuse
WEBUVM RAL is an object-oriented model for registers inside the design. To access these design registers, UVM RAL provides ready-made base classes and APIs. Some of the RAL model features are: Just like design, it supports different register attributes like R/W, RO, WO, W1C, etc. Supports two different paths for register access, frontdoor and ...
I2C Interface Timing Specifications and Constraints - Design And …
WEBI2C (Inter-Integrated Circuit) is a serial communication bus interface connection protocol used by devices. Philips Semiconductor created it at first in 1982. The protocol is now widely used for short-distance communication. It uses a two-wire interface with a bidirectional serial data line (SDA) and a unidirectional serial clock line (SCL).
Reduce ATPG Simulation Failure Debug Time by Understanding …
WEBATPG (Automatic test pattern generation) is the process of generating the test vectors for the particular test mode to check the manufacturing defects, which is further used by simulation tools for validation. ATPG is performed on scan inserted design and the SPF generated through scan insertion. Simulation is the later stage after ATPG, for ...
A Guide on Logical Equivalence Checking - Design And Reuse
WEBA Guide on Logical Equivalence Checking - Flow, Challenges, and Benefits. By Pratik Patel, Prathmesh Oza and Rakesh Parmar (eInfochips) Introduction. The VLSI design cycle is divided into two phases: Front-end and Back-end. Front-end covers the architectural specifications, coding and verification, whereas back-end involves the physical ...